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نویسندگان
چکیده
High-level synthesis is the process of translating a high-level program like specification of the behavior of a digital circuit into a structural design in terms of interconnected set of P..egisterTransfer level components. Component selection and pipelining (CS&P) is one of the important problems in HLS. The time complexity of the exhaustive search algorithm for this problem is exponential. In this paper, we investigate the application of Stochastic Evolution (SE) for solving component selection and pipelining and compare it with simulated annealing (SA). A realistic component library with multiple implementations of o.perators is used for component selection. Pipelining is done based on the constraints of latency and pipestage delay that are specified. Experimental results on different types of DFG's are reported.
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